> Vocation > Methodology > Tools

Vocation _________________________________________________TOP PAGE__

The ID MOS R&D team develops mixed-signal integrated circuit, mainly for specific applications. The expertise acquired for System On Chip (SOC) design, based on micro-controllers, requires multiple engineering profiles for hardware/firmware/software development. One key of success is based on optimized communication rules, therefore we use our own tested methodology.

Methodology ______________________________________________TOP PAGE__

Developments are based, at first, on the high skill of our engineers, nevertheless Industrialization needs more. To optimize the communication and the productivity, ID MOS uses state of the art tools and checklist documents, accumulating years of experience.

The methodology is based on the ASIC development plan document. It guarantees significant reductions in overall development time, coupled with a higher level of confidence in the planned schedule.

Advantage :
- To cover all the tasks from Specification down to Industrialization
- To secure the objective with a tested methodology
- To take into account and minimize risks
- To schedule the tasks with appropriate resources
- To communicate regularly on project progress
- To be in phase with the planning based on Milestones and Reviews .

Tools ______________________________________________TOP PAGE__

ASIC development tools based on CADENCE :

- Ambit - Ncsim
- Composer - Analog Artist - SpectreS - Spectre RF
- Virtuoso
- Silicon Ensemble
- Diva

FPGA development tools:

- Fondation (XILINX)
- MaxPlus (ALTERA)
- 8040K FPGA Integrated Development System V7.2 (ATMEL)