The ID MOS R&D team develops mixed-signal integrated circuit, mainly for specific applications. The expertise acquired for System On Chip (SOC) design, based on micro-controllers, requires multiple engineering profiles for hardware/firmware/software development. One key of success is based on optimized communication rules, therefore we use our own tested methodology.
Developments are based, at first, on the high skill of our engineers, nevertheless Industrialization needs more. To optimize the communication and the productivity, ID MOS uses state of the art tools and checklist documents, accumulating years of experience.
The methodology is based on the ASIC development plan document. It guarantees significant reductions in overall development time, coupled with a higher level of confidence in the planned schedule.
ASIC development tools based on CADENCE :
- Ambit - Ncsim
FPGA development tools:
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