The microchip Final Test is the very last electrical verification of your ASIC. It guarantees the chip integrity though plastic encapsulation and allows temperature testing. This last control, complementary to the wafer test, takes part of the global testability strategy ensuring a global coverage in the end. In the same way as wafer probing, Final Test is prescribed by the project team during the chip design and deployed by the test-engineering department, on various platforms.
Monitoring the Quality of Manufacturing is consolidated by IDMOS’ own Product and Quality Insurance teams. The control of production indicators is done in real-time, with each involved subcontractor, on a by-lot basis. The whole manufacturing process is organized upon control-card monitoring, for which automatic alert levels are revised quarterly. Continuous improvement principles are handled by local Product Managers, who monitor indicator trends, investigate issues related to marginal lots and generate pre-delivery certificates, under the direct supervision of ID MOS Product team.
In many application fields, especially automotive, avionics or medical, the circuit Qualification is required prior to any production launch. Based on AECQ10, JEDEC or ESCC9000 standards, we apply the related specific test flows on the microchips. Our test facilities include pre-conditioning, tests in high-stress environment ((TC, HAST, ESD, EOS) and accelerated aging tests (burn-in, ELFR, HTOL). Deviations and failures are recorded and analyzed with the active support of SERMA Technologies laboratory, in the process of minimizing the manufacturing defect rate.
During the manufacturing of the microchip, the Foundry controls its process parameters by performing several pre-delivery parametric measurements on each wafer. Downstream of the production process, we make a comprehensive functional and parametric test in order to guarantee the product performances. Performed at wafer level (EWS), this die-unitary test allows parametric recording and further analysis techniques such as statistical sorting (part average testing), as part of the global zero-defect process.
The Wafer probing is the outcome of our ASIC design methodology « design for testability », which integrates in each microcircuit a dedicated set of devices for in situ test (BIST) or specific architectures to enhance external tester verifications. During that manufacturing operation, calibration or individual customization can take place.
All our Production subcontractors are ISO9001, ISO14001 certified, and ISO/TS16949 for the most strategic ones. ID MOS regularly conducts Quality and Line audits in order to better master the processes and minimize the Product risks. Continuous improvement is managed by action plans at each production steps in order with the strong philosophy of improving productivity and Quality level.