| ASIC | “Application Specific Integrated Circuit”: it is a silicon microchip which is developed from a product specification. An ASIC is distinct from a « standard IC » proposed by traditional semiconductor manufacturers as it perfectly matches the application. |
| BIST | “Built-in Self test”: it is an auto-test which is embedded in the microchip and allows in situ testing in operation. |
| ELFR | “Early life failure rate”: it is the amount of youthful failing showed by a product |
| EOS | “Electrical Over-Stress”: electrical stress suffered by a microchip when submitted to extreme voltages or currents compared to the ones of its normal operation. ESD is an example of EOS. |
| ESD | “Electro Static Discharge” conducted to a microchip by man or machine. It can be by direct contact or by arcing in air. |
| EWS | “Electrical Wafer Sort”: usually defines the electrical test using probing needles, which is performed on a microchip as it is in wafer form. |
| HAST | “Highly accelerated stress test”: microchip test under high moisture environment |
| HTOL | “High-temperature operating life” : test which determines the intrinsic reliability of a product. The microchip is tested, during a long time, in a temperature and voltage environment beyond its normal operating conditions. |
| SEE | “Single Event Effect”: generic term which describes a functional hazard shown by a microchip when submitted to a ionizing particle. |
| SEFI | “Single Event False Interrupt”: disturbance created by a ionizing particle and which alters the operation sequencing and can lead to an unexpected lock state. |
| SEL | “Single Event Latch-up”: latch-up phenomenon when submitted to ionizing particles |
| SET | “Single Event Transient”: disturbance created by a ionizing particle and which impacts the sensitive nodes of a microchip (analog functions, combinatorial logic blocks …) |
| SEU | “Single Event Upset”: disturbance created by a ionizing particle and which alters the states of memory-like devices (memories, Flip/Flops, Latches…) |
| TC | “Thermal Cycling”: stress test between 2 temperatures which determines the thermal robustness of a technology |
